MODELING OF TRAPPED PLAMA MODE OSCILIATIONS IN AP+ N – N+ SILICON DIODE. Nigerian Journal of Technology, [S. l.], v. 3, n. 1, p. 1–14, 2002. DOI: 10.4314/njt.31.335. Disponível em: https://nijotech.com/index.php/nijotech/article/view/335. Acesso em: 16 apr. 2026.